The present invention relates to fabrication of flash memory devices, and particularly to a method of improving etching profile of floating gates for a flash memory.
Semiconductor memory devices are commonly available in various forms, such as EPROMS, EEPROMS, and flash memory devices. Currently, flash memory, such as a split gate flash memory is widely applied in large capacity non-volatile memory technology. Typically, the split gate flash memory comprises a polysilicon floating gate for charge storage and a polysilicon control gate to control the charge storage. The floating gate is usually disposed under the control gate. The control gate is connected to a word line, while the floating gate is not connected to other wires or components. The erase performance of a split gate flash memory is primarily determined by the tip portion of the floating gate and the thickness of the inter-poly oxide between the floating gate and the control gate. As is known in the art, the sharper the tip portion of the floating gate, the faster the erase speed of the memory cell. That is, the profile of the tip portion of the floating gate determines the speed at which electrons are transferred between the floating gate and the control gate of the split gate flash memory. Moreover, poor profile of the floating gate, for example, an undercut profile or a footing profile, may change the threshold voltage, resulting in undesired electrical properties. Accordingly, profile control is an important factor for flash memory fabrication.
In order to improve the etching profile of the floating gate, several methods are proposed. In U.S. Pat. No. 5,851,926, Kumar et al. provide a method for etching transistor gates using a hard mask, which employs an etch composition comprising NF3, CL2 and HBr for etching transistor gates to achieve profile control. Moreover, in U.S. Pat. No. 6,235,214, Deshmukh et al. provide a method of etching silicon using a gas mixture comprising fluorine and oxygen to etch a silicon substrate and control the etching profile. Moreover, in U.S. Pat. No. 6,509,228, Sun et al. provide a method of forming floating gates for flash memory, which employs two-step etching procedure to improve the sidewall profile of the floating gate. However, the use of etching gases to achieve profile control may result in damage to the hard mask of the thick oxide with bird's beaks, reducing reliability of the memory devices.
Another conventional method for etching profile controlling is to control the process power. However, power control may lower the bombarding effect during etching, increasing the etching time.